Binary bypassable arithmetic linear module

ABSTRACT

A bypassable module for performing an arithmetic linear function is disclosed. The module utilizes well-known binary elements to construct a novel combination thereof that given three multibit binary input signals C, D, X and the single bit binary input signal b generates the alternative output functions

United States Patent Ellison [75] Inventor: James T. Ellison,Minneapolis,

Minn.

[73] Assignee: Sperry Rand Corporation, New

York, NY.

[22] Filed: Feb. 20, 1973 [21] App]. No.: 333,833

[52] US. Cl 235/156, 235/152, 307/207 [51] Int. Cl. G06f 7/38 [58] Fieldof Search..'... 235/152, 156, 175, 153 AC; 307/207 [56] References CitedUNITED STATES PATENTS 3,291,974 12/1966 Even 235/152 X 3,562,502 2/1971Kautz 235/152 3,584,205 6/1971 Malaby et al. 235/152 3,619,583 11/1971Arnold 3,731,073 5/1973 Moylan 235/152 June 18, 1974 PrimaryExaminer-Malcolm A. Morrison Assistant Examiner-James F. GottmanAttorney, Agent, or FirmKenneth T. Grace 1 ABSTRACT Cifb=O CX+Difb=l.

Additionally, disclosed is a linear tree incorporating a plurality ofsuch modules for generating a polynomial of a degree that is determinedby the number of modules not bypassed.

2 Claims, 5 Drawing Figures Cif b =0 CX+D ifb=l SHEET 2 [1F 2 BINARYBYPASSABLE ARITHMETIC LINEAR MODULE BACKGROUND OF THE INVENTION In thedata processing field in which complex arithmetic operations areperformed it is desirable that the arithmetic unit be sufficientlyversatile to perform all arithmetic operations while having a sufficientmodularity to permit the construction thereof of a minimum number ofdifferent types of modules. Additionally, it is desirable that suchmodules be constructed of wellknown binary elements in large scaleintegration (LSI) arrays to utilize the fastest and most economicalfeatures of the present state of art.

In the prior art there are proposed various algorithms whereby anarithmetic linear module having the input signals a, b, x and producingthe output signals ax b can be used iteratively to generate nearly everyfunction that is required for the arithmetic unit of a data processingsystem. Such proposed algorithms for dividing, computing the squareroot, integrating and tracking as well as algorithms for nonlinearfunctions. Thus, entire arithmetic units can be synthesized by theiterative use of such arithmetic linear modules. It is thus an object ofthe present invention to provide an arithmetic linear module that mayutilize such algorithms and that may be fabricated in LSI arrays whilepermitting the bypassing of one or more of such modules if such one ormore modules are defective. Thus, LSI arrays of maximized reliability,yield, and failure recovery capabilities and minimized electronicredundancy and complexity are provided while yet performing the desiredarithmetic operations.

SUMMARY OF THE INVENTION signal b, the alternative output signals Cifb=Thus, if it is determined that the arithmetic linear module isdefective, i.e., not capable of generating the desired CX D outputsignal upon the enabling thereof of the input signal b 1 such arithmeticlinear module may be disabled by the input signal b 0 whereby thebypassed operation is performed by another cascaded binary bypassablearithmetic linear module in an LSI array of such binary bypassablearithmetic-linear modules. Accordingly a tree of such binary bypassablearithmetic linear modules may be constructed, which tree includes one ormore of such binary bypassable arithmetic linear modules than are knownto be required to perform the desired arithmetic operation, such thatlarge quantity production runs of such LSI arrays may be economicallyfabricated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of thebinary bypassable arithmetic linear module of the present invention.

FIG. 2 is a block diagram of the arithmetic linear module utilized toimplement the module of FIG. 1.

FIG. 3 is a block diagram of the bypass switch utilized to implement themodule of FIG. 1.

FIG. 4 is an LSI array of the modules of FIG. 1.

FIG. 5 is a block diagram of the power-of-X generator utilized toimplement the array of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT With particular reference toFIG. 1 there is presented an illustration of a block diagram of thebinary bypassable arithmetic linear module and the symbol therefor ofthe present invention. Binary bypassable arithmetic linear module 10consists of an arithmetic linear module l2 and a bypass switch 14.Arithmetic linear module 12 receives three multibit binary input signalsC, D, X and generates the output signal CX D. The output signal CX Dfrom the arithmetic linear module 12 and the input signal C are boththen coupled as input signals to the bypass switch 14 which provides,under control of a single bit third binary input signal b, thealternative output signals Cifb=0 fCX+Difb=l.

With particular reference to FIG. 2 there is presented a block diagramof the arithmetic linear module 12 and the symbol therefor utilized toimplement module 10 of FIG. 1. Arithmetic linear module 12 is comprisedof two well-known binary arithmetic elements, binary multipler 16 andbinary adder 18. Binary multiplier 16 receives two multibit binary inputsignals C, X and generates the output signal CX. The output signal CXfrom the binary multiplier 16 and a third multibit binary input signal Dare both coupled as input signals to the binary adder 18 which generatesthe output signal CX D.

With particular reference to FIG. 3 there is presented an illustrationof a block diagram of the bypass switch 14 that is utilized to implementmodule 10 of FIG. 1. Bypass switch 14 may consist of four well-knownBoolean elements: AND gates 20, 22; Inverter 24; and, OR gates 26. ANDgates 20 receive the multibit binary input signal CX D and the singlebit binary input signal b while and gates 22 receive the multibit binaryinput signal C and through Inverter 24 the complement of the inputsignal b i.e., F. The output signals from AND gates 20, CX D if b 1 or Cfrom AND gates 22 if b 0 are coupled as first and second multibit binaryinput signals to OR gates 26 which emit the output signals CX D or C,alternatively, under control of the single bit binary input signal b.

As stated hereinabove the present invention is directed toward a methodof implementing an LSI array for implementation in the arithmeticsection of a data processing system. The preferred LSI array should,using various algorithms, be capable of generating nearly everymathematical function. It should permit the use thereof even thoughcertain portions thereof are defective or faulty. The binary bypassablearithmetic linear module 10 of the present invention may be utilized tofabricate an LSI array that meets these requirements.

With particular reference to FIG. 4 there is presented an illustrationof an L8] array 40 that incorporates a plurality of modules 10 and thatis capable of functioning even though one or more modules 10 are faulty.Array 40 is a linear tree that incorporates a plurality of modules 10each of which because of its bypass feature may, if upon productiontesting be found to be faulty, permit the multibit input signal C topass through unmodified to the next cascaded unbypassed module 10. Theonly requirement being that a sufficient number of surplus modules 10 beprovided in array 40 to compensate for the maximum number of faultymodules 10, e.g., modules 10a, 10b, 10c, 10d, 10e, 10f, that can beexpected to be realized in the production thereof.

To implement the desired algorithms, array 40 may include a plurality ofpower-of-X generators 50; FIG. is an illustration of the block diagramand symbol therefor of a well-known generator 50 having multibit firstand second binary input signals X and p for generating the multibitbinary output signal X". Using an array 40 of 27 modules and threegenerators 50 the array 40 is capable of generating the polynomial ofdegree 27, i.e.,

d d x d x (1 x d x.

However, assuming that a certain number of such modules 10 in theproduction array 40 would be faulty, e.g., assume that a maximum of sixmodules 10 would be faulty, array 40 would be designed to be capable ofgenerating the polynomial of degree 21, i.e.,

do d x (1 x dgx dg x With the design capability of array 40 being, ie,the generation of the polynomial degree 21, the array 40 would be testedfor faulty modules 10 and such faulty modules 10, plus any othernonfaulty modules 10 to total six modules 10, would be wired to receiveon their single'bit input signal b a logic 0 while the remaining 21modules 10 would be wired to receive on their single bit input signal ba logic 1.

Because of the bypassable feature of the modules 10, a linear tree ofmodules 10 has a functional capability depending on only its number ofunbypassed modules 10 not on their location within the linear tree.Thus, if the capability desired requires k modules 10, provision of jextra modules 10 provides for up to j faulty modules 10 anywhere in thecascaded portions of the linear tree. Failure of a linearly cascadedmodule 10 that is in a linear cascaded branch 41, 42, 43, 44 of thelinear tree 40 saves the entire branch while failure of a bifurcatingmodule 10g, 10h, 10j (a module 10 receiving both C and D input signalsfrom other branches) saves the branch that it bypassed (input signal C)but loses the other branch (input signal D). However, additional modules10 could be provided to accommodate the loss a bifurcating module 10.Thus, it can be seen that an array of the bypassable arithmetic linearmodule 10 of the present invention can be implemented in an LS1 lineartree to generate a polynomial of any desired degree while providing forthe loss of faulty modules 10 within the array.

What is claimed is:

l. A binary bypassable arithmetic linear module, comprising: a binaryarithmetic linear module, comprising;

a binary multiplier having the binary input signal C as a first inputsignal and the binary input signal X as a second input signal forgenerating the binary output signal CX;

a first binary adder having the binary input signal D as a first inputsignal and said binary output signal CX as a second input signal forgenerating the binary arithmetic linear module output signal CX D; abinary bypass switch, comprising;

a first binary AND gate having said binary arithmetic linear moduleoutput signal CX D as a first input signal and a binary signal b as asecond input signal for emitting said binary arithmetic linear moduleoutput signal CX D only if said binary signal b an inverter having saidbinary signal b as an input signal b for generating an inverter outputsignal b;

a second binary AND gate having said inverter output signal b as a firstinput signal and said binary input signal C as a second input signal foremitting said binary input signal C only if said inverter output signalb l;

a binary OR gate having as a first input signal said binary input signalC as emitted from said second binary AND gate and having as a secondinput signal said binary arithmetic linear module output signal CX D asemitted from said first binary AND gate for emitting, as the binarybypassable arithmetic linear module output signal, said bindaryarithmetic linear module output signal CX D if said binary signal b 1,or, alternatively, said binary input signal C if said inverter outputsignal b l.

2. A binary bypassable arithmetic linear module,

comprising:

a multibit binary arithmetic linear module, comprising;

a multibit binary multiplier having the multibit binary input signal Cas a first input signal and the multibit binary input signal X as asecond input signal for generating the multibit binary multipliermultibit binary output signal CX;

a first multibit binary adder having the multibit binary input signal Das a first input signal and said multibit binary multiplier multibitbinary output signal CX as a second input signal for generating themultibit binary arithmetic linear module multibit binary output signalCX D; a multibit binary bypass switch, comprising;

a first multibit binary AND gate having said multibit binary arithmeticlinear module multibit binary output signal CX D as a first input signaland a single-bit binary signal b as a second input signal for generatingthe first multibit binary AND gate multibit binary output signal CX Donly if said single-bit binary signal b 1;

an inverter having said single-bit binary signal b as an input signal bfor generating an inverter single-bit binary output signal b a secondmultibit binary AND gate having said inverter single-bit binary outputsignal b as a first input signal and said multibit binary input signal Cas a second input signal for generating the second multibit binary ANDgate multibit binary output 3 ,81 8 ,202 5 6 signal C only if saidinverter single-bit binary outa second input signal for generating themultibit bi- P b 1; nary bypassable arithmetic linear module multibit amultibit binary OR gate having said second multibit bina out ut Si nal Cif 5 l or atemativel C X binary AND gate multibit binary output signal Cas p g a first input signal and said first multibit binary 5 D If b ANDgate multibit binary output signal CX D as v UNITED STATES PATENT OFFICECERTIFICATE OF CORRECTION 3,818,202 v June 18,- 1974 Patent No. DatedInventor(s) James T. Ellison It is certified that error appears in theabove-identified patent and that said Letters Patent are herebycorrected as shown below:

Claims 1 and 2, should appear as shown on the attached sheets.

Signed and sealed this 14th day of January 1975.

EA Arrest:

Mace! M'. snssofi JR. Attesting Officer C.... MARSHALL DANN CpmmissionerOf Patent 5 USCOMM'DC 60376-P59 \LS GOVERNMENT PRINT NG OFFICE: B69- 930FORM PO-IOSO (10-69) Patent No. 3,818,202 I P June 18, 1974 I 1 Page 2 Il. A binary bypassable arithmetic linear mgdule, comprising: I I

binary arithmetic linear module, comprising;

I a binary multiplier having the binary input signal C as a first inputsignal and the binary in'putsignal X as a second input signal forgenerating the binaryoutput signal CX; U v I a first binary adder havingthe binary input signal D as a first input signal and said binary outputsignal CX as a second input signal for V generating the binaryarithmetic linear module output signal CX D;

a binary bypass switch, comprising;

I a first binary AND gate having said binary arithmetic linear moduleoutput signal CX D as a-first input signal and a binary signal b as asecond input signal for emitting said binary arithmetic linear moduleoutput signal CX D only if said binary signal b 1;

an inverter having said binary signal b as an input signal b forgenerating an inverter output signal 5;

r a second binary AND gate having said inverter output signal 6 as afirst input signal and said binary input signal C as a second inputsignal for emitting said binary input signal c only if said inverteroutput signal 1.:

June 18, 1974 Patent No. 3,818,202

I Page '3 said binary input signal C if said inverter output signal S 1.

A binary bypassable arithmetic linear module,

canprising:

a' lnultibit binary arithmetic linear module, comprising;

a multibit binary multiplier having the multibit binary input signal Cas a first input signal and the multibit binary input signal X as asecond input signal for generating the multibit binary multipliermultibit ''binazy output signa CX: I

a first multibit ,binary adder having the multibit, binary input signalD as a first input signal and said multibit binary multiplier binaryoutput signal (3X as a second input signal for generating the multibitbinary arithmetic linear module multibit binary output signal CX D; I

. a multibit binary bypass switch, comprising;

- a first multibit binary AND gate having said I multibit binaryarithmetic linear module multibit binary output signal CX D as a firstinput signal and a single-bit binary signal has a second input signalfor generating the first multibit binary AND gate multibit binary outputsignal CX +'D only if said single-bit binary signal an inverter havingsaid single-bit binary signal b as an input signal b for generating aninverter single-bit binary output signal b,-

a second multibit binary AND gate having said inverter single-bit binaryoutput signal 1 as a first input. signal and said multibit binary inputsignal C as a second input signal for generating the second multibitbinary gate multibit binary output signal c only if said I invertersingle-bit binary output signal I? l;

June 18, 1974 Patent No. 3,818,202

. Page, 5

a mu'ltibit binary OR gate having said second multibit binary AND gatemultibit binary output signal C as a first input signal and said firstmultibit biriary AND gate multibit binary output signal CX D as a secondinput signal for v generating the multibit binary bypassable arithmeticl'ine'ar module multibit binary output signal C if 5 1, or,alternatively,

1. A binary bypassable arithmetic linear module, comprising: a binaryarithmetic linear module, comprising; a binary multiplier having thebinary input signal C as a first input signal and the binary inputsignal X as a second input signal for generating the binary outputsignal CX; a first binary adder having the binary input signal D as afirst input signal and said binary output signal CX as a second inputsignal for generating the binary arithmetic linear module output signalCX + D; a binary bypass switch, comprising; a first binary AND gatehaving said binary arithmetic linear module output signal CX + D as afirst input signal and a binary signal b as a second input signal foremitting said binary arithmetic linear module output signal CX + D onlyif said binary signal b 1; an inverter having said binary signal b as aninput signal b for generating an inverter output signal b; a secondbinary AND gate having said inverter output signAl b as a first inputsignal and said binary input signal C as a second input signal foremitting said binary input signal C only if said inverter output signalb 1; a binary OR gate having as a first input signal said binary inputsignal C as emitted from said second binary AND gate and having as asecond input signal said binary arithmetic linear module output signalCX + D as emitted from said first binary AND gate for emitting, as thebinary bypassable arithmetic linear module output signal, said bindaryarithmetic linear module output signal CX + D if said binary signal b 1,or, alternatively, said binary input signal C if said inverter outputsignal b
 1. 2. A binary bypassable arithmetic linear module, comprising:a multibit binary arithmetic linear module, comprising; a multibitbinary multiplier having the multibit binary input signal C as a firstinput signal and the multibit binary input signal X as a second inputsignal for generating the multibit binary multiplier multibit binaryoutput signal CX; a first multibit binary adder having the multibitbinary input signal D as a first input signal and said multibit binarymultiplier multibit binary output signal CX as a second input signal forgenerating the multibit binary arithmetic linear module multibit binaryoutput signal CX + D; a multibit binary bypass switch, comprising; afirst multibit binary AND gate having said multibit binary arithmeticlinear module multibit binary output signal CX + D as a first inputsignal and a single-bit binary signal b as a second input signal forgenerating the first multibit binary AND gate multibit binary outputsignal CX + D only if said single-bit binary signal b 1; an inverterhaving said single-bit binary signal b as an input signal b forgenerating an inverter single-bit binary output signal b; a secondmultibit binary AND gate having said inverter single-bit binary outputsignal b as a first input signal and said multibit binary input signal Cas a second input signal for generating the second multibit binary ANDgate multibit binary output signal C only if said inverter single-bitbinary output signal b 1; a multibit binary OR gate having said secondmultibit binary AND gate multibit binary output signal C as a firstinput signal and said first multibit binary AND gate multibit binaryoutput signal CX + D as a second input signal for generating themultibit binary bypassable arithmetic linear module multibit binaryoutput signal C if b 1, or, alternatively, CX + D if b